1. Field of the Invention
The present invention relates to a cache memory and, more particularly, to a cache memory capable of using idle tag memories of a tag memory array after reconfiguration.
2. Description of the Related Art
A conventional processor generally includes a core and a cache memory. The core is used to execute programs. The cache memory includes a cache controller and a plurality of cache ways. Each cache way includes a data memory and a tag memory for storing data frequently used by the core.
Most of conventional cache memories includes the function of a scratchpad memory (SMP) for predicting the execution time while reducing the power consumption. The scratchpad memory can be in the form of a dedicated memory which increases the costs. Thus, reconfigurable memories are developed, examples of which have been disclosed in EP 1111511 A1 entitled “Cache with Multiple Fill Modes” and disclosed by Zhiguo Ge, Weng-Fai Wong, and Hock-Beng Lim, “DRIM: A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems”, ISBN 978-3-9810801-2-4; 2007 Design, Automation and Test in Europe Conference and Exposition.
However, the addresses in the scratchpad memories are fixed after reconfiguration, such that the access of the tag memories in the cache ways can be ignored. As a result, the tag memory array after reconfiguration (about 6.25-12.5% of the whole cache memory capacity) become idle and is not used, leading to a waste of the storage resource. In a conventional approach, the number of tag memories is reduced to improve this situation, but the flexibility tolerance of reconfiguration is also reduced.
In view of the disadvantages of the conventional techniques in actual use, a need exists for an improved cache memory to increase the utility.